1. Field of Invention
This document relates to a display device and a method for controlling gate pulse modulation thereof.
2. Related Art
A liquid crystal display (“LCD”) has been widely applied due to its lightweight, thin profile, lower power consumption driving, and so on. Such an LCD has been employed as a portable computer such as a notebook PC, an office automation device, an audio/video device, an indoor/outdoor advertisement display device or the like. The LCD displays images by controlling an electric field applied to LC cells to adjust a light from a backlight.
An active matrix type LCD comprises an display panel assembly provided with thin film transistors (“TFTs”) which are disposed at the respective pixels and switch data voltages supplied for pixel electrodes, a data driving circuit which supplies the data voltages for data lines in the display panel assembly, a gate driving circuit which sequentially supplies gate pulses (or scan pulses) for gate lines in the display panel assembly, and a timing controller which controls operation timings of the above-described driving circuits.
In the active matrix type LCD, a voltage charged in the LC cell is influenced by a kickback voltage (or a feed through voltage) ΔVp generated due to a parasitic capacitance in the TFT. The kickback voltage ΔVp is given as the following equation (1).
                              Δ          ⁢                                          ⁢          Vp                =                              Cgd                          Clc              +              Cst              +              Cgd                                ⁢                      (                                          V                ⁢                                                                  ⁢                G                ⁢                                                                  ⁢                H                            -                              V                ⁢                                                                  ⁢                G                ⁢                                                                  ⁢                L                                      )                                              (        1        )            
Where “Cgd” represents a parasitic capacitance generated between a gate terminal of the TFT connected to the gate line and a drain terminal of the TFT connected to a pixel electrode in the LC cell, and “VGH−VGL” represents a difference between a gate high voltage and a gate low voltage of the gate pulse supplied for the gate line.
The kickback voltage ΔVp may alter a voltage applied to the pixel electrode in the LC cell, thereby showing a flicker, an afterimage, a color deviation, or the like. As methods for reducing the kickback voltage ΔVp, there is a gate pulse modulation (“GPM”) method for modulating the gate high voltage VGH at the falling edge of the gate pulse. FIG. 1 is a waveform diagram illustrating an example where a gate pulse is not modulated (NO GPM) and an example where a gate pulse is modulated (GPM). The gate high voltage VGH is lowered at the falling edge of the modulated gate pulse.
The timing controller generates a gate pulse modulation control signal (hereinafter, referred to as a “FLK signal”) used to control modulation timings for the gate pulses along with gate shift clocks used to shift a gate start pulse GSP. Generally, the gate shift clocks are generated as clocks of two or more phases which are delayed sequentially, and the FLK signal is synchronized with each clock. A gate pulse modulation circuit in the gate driving circuit modulates the gate high voltage VGH in synchronization with the FLK signal.
As shown in FIG. 2, if an N-th (where N is a positive integer) gate pulse Nth GP and a (N+1)-th gate pulse (N+1)th GP overlap each other, the gate high voltage VGH is lowered not only at the edge of the gate pulse but also at a pulse-width duration where the gate high voltage VGH is required to be maintained. In FIG. 2, the reference numeral “VGHM” denotes a gate high voltage modulated in synchronization with the FLK signal. The modulation is performed at the duration where the gate high voltage VGH is required to be maintained, and this causes a current consumption to be increased and further a charging ratio of the data voltage in the display panel assembly to be reduced.
In order to solve this problem, there may be a consideration of a method where the FLK signal is divided into two or more phases and the gate pulse modulation circuits are configured independently from each other for each FLK signals. However, this method has problems in that the number of the FLK signals is increased to thereby add circuits in the timing controller and increase output pins of the timing controller, and the number of the FLK signals is increased as an overlap duration of the gate pulses are lengthened.